The present invention relates to a method of measuring an overlay offset and, more particularly, to a method of measuring the overlay offset of a resist pattern formed on a semiconductor wafer in, e.g., a lithography step for the production of a semiconductor device.
It is a common practice with the production of a semiconductor device to measure the overlay offset of a resist pattern from a pattern existing on a semiconductor wafer. Specifically, when a wafer covered with photoresist is exposed to a desired mask pattern by a demagnification projection aligner, it is necessary to expose a preselected part of the existing pattern to the mask pattern with accuracy. Therefore, the position of the pattern existing on the wafer must be measured first.
To measure the position of the pattern existing on the wafer, an alignment sensor is mounted on the projection aligner in order to sense alignment marks provided on the wafer beforehand. Specifically, several sample marks or points of the surface of the wafer are measured, and then the resulting coordinates data are statistically processed in order to produce control parameters for driving a wafer stage. The wafer sensed by the alignment sensor is exposed under exposure position control based on the calculated control parameters. The exposed wafer is developed in order to form a desired pattern thereon. Subsequently, the overlay offset is measured in order to determine whether or not the positional deviation of the resist pattern from the pattern existing o n the wafer is less than a device design standard. Overlay offsets exceeding the design standard would bring about various defects. Today, the allowable overlay offset is strictly limited to around 0.1 .mu.m, so that highly accurate alignment and highly accurate measurement of offsets are essential. In light of this, the current trend is toward the use of an automatic measuring device having an image processing function. Usually, the automatic measuring device processes an exclusive measurement pattern read out of several points (five to ten points) of the wafer surface.
As for the overlay offset, it has been customary to test all the wafers of a lot (first testing method hereinafter) or to test only sample wafers (second testing method hereinafter), depending on the kind of devices and the step.
Because the first testing method measures all the wafers of a lot in order to determine their overlay offsets, it insures that all the wafers of the lot have overlay offsets lying in an allowable range. However, the problem with the first testing method is that it increases the testing time for a single lot. For example, assume that a single lot has twenty-five wafers, and that each wafer is measured at five spaced points (in X and Y directions at each point). Then, the total measuring time is as long as about 20 minutes to 30 minutes. Such a period of time is about 50% of the total period of time necessary for a demagnification protection aligner to handle the same number of wafers. Therefore, assuming that testing all the wafers is a standard method, then a great number of automatic measuring devices must be used. In addition, an increase in processing time adversely influences the step progress of the lot.
The second testing method measures the overlay offset with, e.g., three sample wafers out of the twenty-five wafers. The three wafers are selected at random. Wether or not the lot is satisfactory is determined on the basis of the overlay offsets of the three wafers. For example, if all the three wafers are satisfactory, the other wafers are also determined to be satisfactory without any measurement, and the entire lot is determined to be satisfactory. If even one of the three wafers is defective, the alignment accuracy of the lot is determined to be ascribable to a low step ability. In this case, the other wafers of the lot are additionally tested, or the entire lot is determined to be defective. The second testing method implements a far higher throughput than the first testing method, but cannot insure that the wafers other than the sample wafers have overlay offsets lying in the allowable range.
As stated above, a first problem with the conventional methods is that the first testing method is low in processing efficiency and increases the processing time because all the wafers of a lot are tested or only sample wafers of a lot are tested at random. This stems from the fact that a system for estimating alignment accuracy lot by lot and selecting an adequate test mode is not available.
A second problem is that in the case of the sampling scheme, the overlay offsets of wafers other than the sample wafers cannot be guaranteed with high accuracy. This is because a system for estimating a distribution of overlay offsets of the entire lot from the measured overlay offsets of sample wafers is not available.